To overcome the need for better thermal and electrical conductivity in semiconductor manufacturing, metals offering better electrical and thermal conductivity such as copper are increasingly used to replace metals with lower conductivity such as aluminium for power metallization. The major hurdle on this way is the structuring of the power metal in FEOL (front end of line) as well as BEOL (back end of line) processes. Metals such as copper cannot be structured using conventional methods (wet or dry etch) due to unavailability of proper etching agents. Therefore, at present stage, during provision of power metallization, metals are structured by a method called dual Damascene, in which a semiconductor workpiece is patterned with open trenches e.g. formed in an oxide layer which are then filled with a thick layer of metal, typically copper, usually overfilling the trenches, and chemical-mechanical planarization (CMP) is used to remove the excess portions of the metal. In order to do so, thicker photo resist or oxide layers, e.g. in the range of 10 μm or more, are used for the structuring process of the metal. The larger thickness of photo resist and its structuring leads to higher costs and, in addition, technical problems with photolithography and resist strips may arise. Furthermore, when copper structures as thick as 50 μm are needed, that conventional manufacturing process reaches its application limit.